摘要
Digital Delay-Locked Loops (DLLs) have been widely used in today's ICs for all kinds of timing control. Even though a digital DLL circuit is much easier to design than its analog counterparts, our prior experience shows that weeks' of efforts, if not months, could still he wasted in order to find a process resilient configuration for a specific DLL requirement. Thus, we propose in this work a cell-based DLL architecture and its compiler. According to a user's demand, our DLL compiler can generate a cell-based DLL circuit in just minutes, it can support easy process migration, and thereby saving a large amount of human efforts spent in tuning DLL designs for different manufacturing processes. Transistor-level simulation has been used to validate its ability in a 0.18 CMOS process and a 90nm CMOS process. It can support input clock frequency up to 1GHz in 0.18 mu m, and 1.25GHz in 90nm.