Comparison of Vertically Double Stacked Poly-Si Nanosheet Junctionless Field Effect Transistors with Gate-all-around and Multi-gate Structure

Meng-Ju Tsai; Kang-Hui Peng; Yu-Ru Lin; Yung-Chun Wu; IEEE

doi:10.1109/VLSI-TSA.2019.8804683

會議論文集

Comparison of Vertically Double Stacked Poly-Si Nanosheet Junctionless Field Effect Transistors with Gate-all-around and Multi-gate Structure

Meng-Ju Tsai, Kang-Hui Peng, Yu-Ru Lin 和 Yung-Chun Wu

2019 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 頁碼.1-2

04/2019

DOI: https://doi.org/10.1109/VLSI-TSA.2019.8804683

摘要

Field effect transistors

Gallium arsenide

Ions

Logic gates

Performance evaluation

Temperature

Three-dimensional displays

This work demonstrates the double-stacked nanosheet (NS) p-channel vertically junctionless field-effect transistors (VJ-FET) with gate all around (GAA) structure. The stacked NS device shows superior electrical properties, including high Ion/Ioff ratio , subthreshold slope (SS) =100mV/dec, and normally off at Vg=0V. More, this work also discusses three different gate structure in electrical properties. The 3D TCAD simulation is applied for analysis of physical characteristics of the proposed devices.

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詳細資料

題名: Comparison of Vertically Double Stacked Poly-Si Nanosheet Junctionless Field Effect Transistors with Gate-all-around and Multi-gate Structure
創作者：: Meng-Ju Tsai - National Tsing Hua University, Hsinchu, Taiwan
Kang-Hui Peng - National Tsing Hua University
Yu-Ru Lin - National Tsing Hua University
Yung-Chun Wu - National Tsing Hua University, Hsinchu, Taiwan
IEEE
出版者: IEEE
總頁數: 2
學術資源類型: 會議論文集
出版日期: 04/2019
出版資訊: 2019 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 頁碼.1-2
語言: 英語

Comparison of Vertically Double Stacked Poly-Si Nanosheet Junctionless Field Effect Transistors with Gate-all-around and Multi-gate Structure

摘要

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詳細資料

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