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DRC Violation Prediction with Pre-global-routing Features Through Convolutional Neural Network
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DRC Violation Prediction with Pre-global-routing Features Through Convolutional Neural Network

Jhen-Gang Lin, Yu-Guang Chen, Yun-Wei Yang, Wei-Tse Hung, Cheng-Hong Tsai, De-Shiun Fu 和 Mango Chia-Tso Chao
Proceedings of the Great Lakes Symposium on VLSI 2023, 頁碼.313-319
ACM Conferences
GLSVLSI '23: Great Lakes Symposium on VLSI 2023
05/06/2023
Web of Science ID: WOS:001042307500061

摘要

Hardware -- Electronic design automation -- Methodologies for EDA -- Software tools for EDA Hardware -- Electronic design automation -- Physical design (EDA)
Design Rule Checking (DRC) is one of the most important metrices in physical design procedure to evaluate quality of a detail route. The prediction of DRC violation (DRV) in the early stage can reduce the iterations of design procedure and improve the efficiency of the physical design closure. Several researchers have applied machine-learning techniques to predict the DRVs of a detail route at different design stages with various input features. In this paper, we proposed a machine learning model to predict DRVs with the information obtained after placement stage. Specifically, we build a ResNet-like CNN model to predict whether a DRV may occur in a targeted grid after detail route. Our features consist of not only quantified placement information but also layout-image features to take pin accessibility into account for better prediction result. Moreover, we apply an under-sampling technique to select critical training samples to improve the training efficiency. A series of experiments have been conducted and the results show that compared with previous works, our prediction result can outperform Fully Convolutional Network (FCN) based approaches.

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https://doi.org/10.1145/3583781.3590216檢視
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