摘要
This paper proposes an electrostatic discharge (ESD) protection in Gallium Nitride (GaN)-on-silicon processes. With well-designed ESD circuits, the drawback of large quiescent current (I Q ) in conventional ESD schemes can be reduced through an area-efficient implementation. In addition, the geometry of GaN devices, specifically the lengths of PGaN (L g ), field plate (FP), and gate shield layer (L_(M)0), can be tuned to effectively reduce the intrinsic gate-to-drain capacitance (C GD ), by tuning the distance from drain to source (L DS ) effectively reduces the on-resistance (R on ). Therefore, the reduction of RC delay greatly improves the response time of the ESD circuit even under low I Q operation. Experimental results show that human body model (HBM) test and machine model (MM) test can be increased to 3kV and 100V, respectively. Moreover, I Q can be reduced to 8.11μA, which is a 222x improvement.