摘要
Plasma process induced wafer arcing phenomena has been a hidden secret in the semiconductor industry for the past 25 years with great impact to production yield for both logic and memory manufacturing. The main mechanism is plasma and wafer surface structure interaction induced arcing excursion [1]. Highly unbalanced bias for certain process steps combined with suitable conducting structure was the main reason for wafer arcing with surface structure variation to determine the frequency of arcing. However, it is not well understood on the impact of the hardware design to provide such driving force at the wafer edge so it is of great interest to explore a possible "hardware design rule" to reduce the arcing frequency from chamber design point of view.