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Effects of Pressure and Bias Voltage on the Phase Noise of CMOS-MEMS Oscillators
Conference proceeding

Effects of Pressure and Bias Voltage on the Phase Noise of CMOS-MEMS Oscillators

Wan-Cheng Chiu, Ming-Huang Li, Chao-Yu Chen and Sheng-Shian Li
2015 JOINT CONFERENCE OF THE IEEE INTERNATIONAL FREQUENCY CONTROL SYMPOSIUM & THE EUROPEAN FREQUENCY AND TIME FORUM (FCS), pp.155-157
IEEE International Frequency Control Symposium
01/01/2015

Abstract

Engineering Engineering, Electrical & Electronic Physical Sciences Physics Physics, Applied Science & Technology Technology Telecommunications
In this work, we present a comprehensive study on the effects of environmental pressure (P) and resonator dc-bias voltage for the phase noise of a monolithic CMOS-MEMS oscillator. In order to access the practical utility of CMOSMEMS oscillators for versatile applications, a double-ended tuning fork (DETF) MEMS resonator oscillator is used as a case study. In the ambient pressure, the oscillation ensues at a minimum V-P = 30V and shows a phase noise (PN) of -86 dBc/Hz at 1-kHz offset and -99 dBc/Hz at 1-MHz offset. On the other hand, a low-V-P CMOS-MEMS oscillator with IC compatible voltage (i.e., V-P = 3V, leading to an equivalent motional impedance R-m of 100 M Omega) is also demonstrated in a vacuum chamber (P < 1 mTorr) with a PN of -94 dBc/Hz at 1-kHz offset and -98 dBc/Hz at 1-MHz offset, respectively.

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