Error estimations of projection-based interconnect model-order reduction techniques

Chia-Chi Chu; Herng-Jer Lee; Wu-Shiung Feng

doi:10.1109/APCCAS.2004.1413072

會議論文集

Error estimations of projection-based interconnect model-order reduction techniques

Chia-Chi Chu, Herng-Jer Lee 和 Wu-Shiung Feng

The 2004 IEEE Asia-Pacific Conference on Circuits and Systems : proceedings, SoC design for ubiquitous information technology, December 6-9, 2004, Tayih Landis Hotel, Tainan, Taiwan, 卷.2, 頁碼.1085-1088 vol.2

2004

DOI: https://doi.org/10.1109/APCCAS.2004.1413072

摘要

Algorithm design and analysis

CMOS process

Computer errors

Error analysis

Fabrication

Guidelines

LAN interconnection

Reduced order systems

Semiconductor device modeling

Transfer functions

Projection-based model reductions become a necessity for efficient interconnect simulations. In order to choose the order of the reduced system that can really reflect the essential dynamics of the original interconnect, the residual error of the transfer function is considered as a stopping criteria. Analytical expressions of this residual error are derived analytically. This approximate transfer function can also be expressed as the original interconnect model with some additive perturbations. These error information provides a guideline for the order selection scheme.

指標

1 檢視次數

詳細資料

題名: Error estimations of projection-based interconnect model-order reduction techniques
創作者：: Chia-Chi Chu - Chang Gung University
Herng-Jer Lee - Chang Gung University
Wu-Shiung Feng - Chang Gung University
出版者: IEEE
學術資源類型: 會議論文集
出版日期: 2004
出版資訊: The 2004 IEEE Asia-Pacific Conference on Circuits and Systems : proceedings, SoC design for ubiquitous information technology, December 6-9, 2004, Tayih Landis Hotel, Tainan, Taiwan, 卷.2, 頁碼.1085-1088 vol.2
語言: 英語

Error estimations of projection-based interconnect model-order reduction techniques

摘要

相關連結

指標

詳細資料

National Tsing Hua University 社交媒體