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First Demonstration of Defect Elimination for Cryogenic Ge FinFET CMOS Inverter Showing Steep Subthreshold Slope by Using Ge-on-Insulator Structure
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First Demonstration of Defect Elimination for Cryogenic Ge FinFET CMOS Inverter Showing Steep Subthreshold Slope by Using Ge-on-Insulator Structure

X.-R. Yu, C.-C. Hsieh, M.-H. Chuang, M.-Y. Chiu, T.-C. Sun, W.-Z. Geng, W.-H. Chang, Y.-J. Shih, W.-H. Lu, W.-C. Chang, …
Technical Digest - International Electron Devices Meeting, IEDM
2023
Web of Science ID: WOS:001693000200141

摘要

Cryogenics Crystallinity Defects FinFET Forecasting Germanium Silicon Substrates Cryogenic measurement Cryogenic temperatures Defect elimination Electrical characteristic Electrical circuit Ge on insulators Germanium-on-insulator Germaniums (Ge) Insulator structure Subthreshold slope CMOS integrated circuits
This work presents experimental electrical characteristics and circuit prediction at cryogenic temperatures (down to 10 K) for three different kinds of germanium (Ge)-based FETs with advanced Fin/GAA structures. Among them, the layer transferred Ge-on-Insulator (GeOI) FinFET significantly improves its I-V characteristic during cryogenic measurements, such as a steeper subthreshold swing at 10K and a better Ion. The developed GeOI fabrication method provides an effective way to eliminate the defects originating from misfit dislocations at the Ge/Si substrate during epitaxial growth, which would be treated as the key to device performance enhancement under 10 K. According to the measured IV at 10 K and circuit prediction, GeOI FinFETs with high Ge crystallinity are strong candidates for High-Performance-Computing (HPC) applications. © 2023 IEEE.

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