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Heterogeneous CFET: A Pathway to CMOS Performance Balance Engineering
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Heterogeneous CFET: A Pathway to CMOS Performance Balance Engineering

X.-R. Yu, W.-H. Lu, S.-W. Chang, W.-H. Chang, D.D. Lu, Y.-J. Lee, T. Maeda, W.-F. Wu, Y.-M. Li 和 Y.-H. Wang
2024 IEEE Silicon Nanoelectronics Workshop, SNW 2024, 頁碼.5-6
2024
DOI: https://doi.org/10.1109/SNW63608.2024.10639243
Web of Science ID: WOS:001309996500003

摘要

Wafer bonding Area reduction High performance characteristics Layer transfer Performance balance Technology nodes Transfer technique CMOS integrated circuits
The CFETs can provide high-performance characteristics with significant area reduction for Å technology nodes. However, mobilities between n/p FETs need to be considered for the performance balance of CMOS. This paper introduces heterogeneous and hetero-orientational CFETs using wafer bonding and layer-transfer techniques. © 2024 IEEE.

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https://www.scopus.com/inward/record.uri?eid=2-s2.0-85203842165&doi=10.1109%2fSNW63608.2024.10639243&partnerID=40&md5=2aac87fbf4de356d8ac694be5797ddab檢視

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