摘要
Power Distribution Network (PDN) are indispensable for modern integrated circuits (ICs), providing supply voltage and ground to transistors. However, the presence of IR-drop, caused by parasitic resistance in power network wires, can degrade circuit performance by reducing noise margins. Previous research tackled IR-drop reduction by refining PDN, but overlooked routing issues leading to circuit timing challenges. This paper proposes a novel framework addressing both concerns. Our approach enhances power network design by strategically adding power stripes to optimize circuit timing, mitigate IR-drop, and alleviate routing congestions. Experimental results demonstrate a 5.8% improvement in total negative slacks compared to the original design.