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Improving Simulation Efficiency of Chiplet Package Solder Bump Reliability Analysis Using Equivalent Beam Model
會議論文集

Improving Simulation Efficiency of Chiplet Package Solder Bump Reliability Analysis Using Equivalent Beam Model

C.E. Chang, Qinghua Su 和 K.N. Chiang
International Conference on Thermal, Mechanical and Multi-physics Simulation and Experiments in Microelectronics and Microsystems (Online), 頁碼.1-5
19/04/2026

摘要

Beams Chiplet Packages Dies Equivalent Beam Finite element analysis Finite Element Method Materials Modeling Multi-Point Constraint Packaging Printing Simulation Soldering Thermo-mechanical analysis Timing
With the recent slowdown in transistor scaling, the semiconductor industry has been actively exploring new technological pathways to sustain performance improvements and cost efficiency. Among these, chiplet-based design has become a central focus, offering a promising route to extend system performance. However, as packaging designs grow increasingly complex and integration density rises, reliability challenges have also intensified.In this study, a 3D Finite Element Analysis (FEA) model is employed to effectively evaluate the reliability of chiplet packages. Due to the structural complexity and large element count of chiplet models, the Global-Local Finite Element Method (FEM) is integrated with the Equivalent Beam Theory to reduce the total number of elements and computational time. Coupled thermo-mechanical simulations are conducted in ANSYS APDL under JEDEC thermal cycling conditions (-40 °C to 125 °C) using SAC305 solder, in order to identify potential failure regions.Although the equivalent beam model effectively predicts failure locations, it still requires a long computation time due to the numerous Multi-Point Constraints (MPC) and convergence issues. Therefore, this study aims to enhance the computational efficiency of chiplet package reliability simulations by optimizing the equivalent beam model while maintaining prediction accuracy.

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