Approximate computing is an emerging design paradigm for error-tolerant applications, such as multimedia processing and neural network acceleration, which enables significant reductions in circuit area, delay, or power consumption through controlled accuracy trade-offs. This paper presents a novel deep reinforcement learning (DRL)-based framework for approximate logic synthesis (ALS) augmented with a backtracking mechanism, aimed at minimizing the area-delay product (ADP) while satisfying error rate constraints. The experimental results demonstrate that our approach can reduce the ADP by up to 92.83%, and 56.79% on average under a 5% error rate constraint.
- Learning to Approximate: Circuit Learning and Deep Reinforcement Learning for Approximate Logic Synthesis with an Error Rate Guarantee
- Chi-Wei Chen - National Tsing Hua UniversityYi-Ting Li - National Tsing Hua UniversityWuqian Tang - National Tsing Hua UniversityYung-Chih Chen - National Taiwan University of Science and TechnologyJian-Meng Yang - Arculus System Co., Ltd.,USChun-Yao Wang (Author) - National Tsing Hua University
- EDAA
- 7
- Conference proceeding
- 20/04/2026
- Proceedings - Design, Automation, and Test in Europe Conference and Exhibition, pp.1-7
- English