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Physical Estimation of Epoxy Flux Pattern Design of Multi-Chip Module Packaging
會議論文集

Physical Estimation of Epoxy Flux Pattern Design of Multi-Chip Module Packaging

K.-W. Chou, C.-Y. Weng, Y.-Y. Zheng, S.-Y. Yang, C.-C. Chan, C.-W. Wang, J.-C. Chuang 和 C.-C. Lee
2026 International Conference on Electronics Packaging and Hybrid Bonding Symposium, ICEP-HBS 2026, 頁碼.287-288
2026

摘要

Epoxy flux FEM Joint Reliability WLCSP Chip scale packages Flip chip devices Microprocessor chips Packaging materials Reliability Soldered joints Soldering Thermal cycling Thermal expansion Thermal fatigue WSI circuits Epoxy Epoxy flux Flux patterns Joint reliability Module packaging Multi chip modules Pattern designs Solder joints Thermal-cycling Wafer-level chip scale packages Packaging
With the rapid development of automotive electronics, artificial intelligence, and mobile applications, electronic packaging faces increasing demands for miniaturization, performance, and environmental sustainability. Although flip-chip packaging is widely adopted in high-density applications, the coefficient of thermal expansion mismatch (CTE) among packaging materials often induces solder joint fatigue under thermal cycling. Conventional underfill can mitigate thermal stress but suffers from long processing time, void formation, and high energy consumption. Unlike conventional underfill, epoxy flux structure selectively encapsulates regions prone to solder joint failure without fully filling the chip-substrate gap. This study establishes a three-dimensional finite element model (3D FEM) to investigate the thermo-mechanical reliability of wafer-level chip-scale packages (WLCSPs) with epoxy flux structure under thermal cycling from -40 °C to 85 °C. The effects of epoxy flux fill height and coverage area on the equivalent plastic strain of SAC305 solder joints are evaluated. The results demonstrate that epoxy flux structure provides effective mechanical reinforcement and improves solder joint reliability in high-density packaging applications. © 2026 Japan Institute of Electronics Packaging.

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https://www.scopus.com/inward/record.uri?eid=2-s2.0-105043719434&doi=10.23919%2fICEP-HBS69241.2026.11550604&partnerID=40&md5=5afbec3cf228558a2ede3650cea7988f檢視

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