摘要
To address increasing demand for bandwidth and Moore's law limitations, innovations in chip and system architectures are crucial. Chiplet technology, heterogeneous integration, and co-packaged optics offer solutions for power and bandwidth challenges in Ethernet switching, AI, and HPC, alongside with SoIC, CoWoS, and InFo technologies. Besides silicon substrates, glass substrates are alternative solutions for advanced packages, based on the low dielectric loss, high thermal stability, and as well as coefficient of thermal expansion approximately silicon material. In addition, through glass vias (TGV) is employed for vertical interconnections of DC signal or RF. In this study, the properties and mechanical performance of copper material used to fill in TGV, are examined. Copper is chosen for superior electrical conductivity, which is crucial for ensuring efficient signal transmission in advanced high-density electronic packaging. Based on the unique material properties of glass substrates and the copper filling, the thermal and mechanical stresses cause potential failure modes. In addition, considered manufacture process and thermal annealing, material properties of TGV before and after annealing are measured from nanoindentation, where each grain size of copper under different conditions compared by the method of electron backscatter diffraction. However, the relationship between stress and strain from nanoindentation is not depicted directly. Therefore, elastoplastic FEA, integrated with Power law, is developed to simulate physical behavior of P -h curve in nanoindentation, validated with experimental measurement. After establishing the modeling, the relationship between temperature-based stress and strain are collected. High-temperature implicit creep model of ANSYS, integrated with strain hardening rule, is developed for creep behavior of copper material in TGV. Additionally, a test vehicle consisting of a filled copper TGV substrate with dimensions of 50 mm in length and 50 mm in width, along with vias of 30 micrometers in diameter, is selected. The optical method of digital image correlation is employed to evaluate the warpage. Finally, a 510 ∼mm × 515 ∼mm area of the TGV substrate is analyzed, and the warpage distribution is estimated based on validated FEA results for mask-less digital lithography technology before vacuum chucking conditions. © 2025 IEEE.