摘要
As monolithic SoC designs face growing performance limitations, heterogeneous 2.5D integration has become a practical alternative, which enables efficient assembly of multiple chiplets, that may use different process technologies. Selecting a suitable process technology for each chiplet is critical for minimizing cost and satisfying constraints on area, power, and thermal issues. In this paper, we propose an approach that efficiently determines the optimal process selection for each chiplet in a heterogeneous 2.5D integration design. Our approach reduces computation time by over 90% on average for a set of benchmarks compared to conventional dynamic programming, while achieving high-quality, constraint-compliant designs.