摘要
An All-Digital Phase-Locked Loop (ADPLL) often uses a multi-segment Digitally-Controlled Oscillator (DCO), thus introducing unnecessary jitter when operating under a more hostile environment due to the segment-jumping problem. Recently, a Ping-Pong architecture has been proposed to cope with this issue. However, the prior Ping-Pong ADPLL still suffers from some delay-mismatch problems due to process variation. In this work, we propose a run-time self-calibration scheme to overcome this problem. Post-layout Monte-Carlo simulation demonstrates that 27.94% peak-to-peak jitter reduction can be achieved.