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Si Multi-Bridge Channel CMOS Inverter with Five Stacked Layers Fabricated from Epitaxial Si0.8Ge0.2/Si Multilayers
會議論文集

Si Multi-Bridge Channel CMOS Inverter with Five Stacked Layers Fabricated from Epitaxial Si0.8Ge0.2/Si Multilayers

W.-Y. Chang, G.-L. Luo, C.-L. Chu, S.-H. Chen, F.-K. Hsueh, B.-Y. Chen, Y.-J. Lee 和 W.-F. Wu
2024 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2024 - Proceedings
2024

摘要

Bridges CMOS integrated circuits Dry etching Atomic layer etching Channel implantation Channel widths CMOS devices Dry etching process Epitaxial Si Etching process N-channel Selective etching Stacked layer Fabrication
This study successfully fabricates a CMOS device with an advanced 5-layer Si multi-bridge channel (MBC) through a highly selective dry etching process explicitly designed for GAA-FET manufacturing. The investigation employs highly selective etching processes, Atomic Layer Etching (ALE), to explore the impact of p-/n-channel implantation with varying channel widths in creating highly stacked multi-bridge channels for advancing CMOS GAAFET technology. © 2024 IEEE.

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https://www.scopus.com/inward/record.uri?eid=2-s2.0-85196724021&doi=10.1109%2fVLSITSA60681.2024.10546459&partnerID=40&md5=fc6c44fc448bc7444b2c485719964a65檢視

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