摘要
In a chiplet design, several dies are integrated through die-to-die interconnects. Technical challenges still exist when it comes to the repair of faulty die-to-die interconnects to boost the overall manufacturing yield. In this work, we aim to perform Built-In Self-Repair (BISR) of small bridging faults occurring to cycle-based interconnects in a chiplet design. We fixed the potential "under-testing" problem in the traditional Pulse-Vanishing Test (PV-test) by adjusting the test pulse width in the test pulse signal. This adjustment involves two steps - the offline adjustment procedure and the on-chip adjustment circuit. The adjusted PV-test scheme can easily support at-speed BISR procedure suitable for arbitrary interconnects in a chiplet design.