摘要
Digital computing-in-memory (DCIM) with multiply and accumulate (MAC) function has been considered as an acceleration engine of deep neural networks (DNNs). A basic DCIM unit with MAC function consists of a bit-multiplication memory (BMM) and an adder tree. A DCIM typically consists of a huge amount of DCIM units for massive parallel computing. Effective modeling and design techniques are needed for designing energy-efficient DCIMs. Also, effective testing techniques are very important for ensuring the quality of DCIM chips. In this paper, design, modeling, and testing techniques for DCIMs with MAC function will be introduced. Firstly, a precision-aware tolerance technique for adder tree circuits is presented, aiming to reduce dynamic power consumption in DCIMs across various DNN applications. Secondly, a scalable and accurate delay modeling framework that accelerates architecture-level optimization for systems integrating DCIM circuits is introduced. Thirdly, a DCIM-FaultSim, the first efficient fault simulator specifically designed for DCIMs is introduced. The DCIM-FaultSim supports a wide range of fault models, covering both conventional memory faults and compute-related faults induced by in-memory bit-level operations. Finally, a novel transparent test scheme for DCIMs is introduced.