摘要
Thermal and mechanical interactions are increasingly critical as advanced wafer nodes drive higher transistor density, I/O count, and power consumption. These factors enlarge package dimensions, creating challenges for applying flip-chip chip-scale packages (FCCSPs) to automotive applications where strict AEC-Q100 reliability standards apply. This study examines a large 17×17 mm exposed-die FCCSP with a coreless substrate developed for automotive-grade SoCs. The fundamental design challenge arises from an inherent thermal-mechanical trade-off: the exposed-die architecture necessary for thermal performance removes the mold compound that serves as a critical mechanical element for suppressing high-temperature concave warpage in large-body packages. This conflict is particularly acute at the 17×17 mm scale, where coreless substrate stiffness is insufficient to resist CTE mismatch-driven bending moments without mechanical compensation from the encapsulant.To resolve this trade-off, finite element modeling (FEM)-guided co-design simultaneously optimized die thickness, mold compound selection, mold cap thickness, and substrate stack-up. This approach achieved warpage below 80 μm under JEDEC reflow conditions-well within the SMT coplanarity requirement-with actual measured results of 47 μm at room temperature and −23 μm at 260°C peak reflow, providing a margin exceeding 30 μm against the SMT process window. The exposed-die architecture provides a direct dissipation path through TIM and heatsink, achieving a 15-20% reduction in junction-to-board thermal resistance (θJB) compared with conventional molded FCCSPs. Under a representative 15 W automotive workload, this translates to a junction temperature reduction of approximately 3-4°C, which directly reduces creep accumulation and IMC growth rates in solder joints, extending fatigue lifetime under automotive thermal cycling loads. Board-level reliability (BLR) tests including TCoB (TC-G: first failure at 1413 cycles, Weibull η = 3352 cycles, β = 3.93), thermal shock, mechanical shock, and vibration confirmed full compliance with AEC-Q100 Grade 2 requirements with no solder joint failure or delamination observed. To the authors' knowledge, this is the first demonstration that large-body FCCSPs on coreless substrates can simultaneously resolve the thermal-mechanical trade-off and achieve Grade 2 automotive reliability, establishing a simulation-validated co-design framework for next-generation automotive SoC packaging.