摘要
TSV-induced delay variations and delay faults in 3D-DRAM ICs can shrink the timing margin between DQ and DQS signals, causing conventional fixed-DQS-timing schemes to fail. This work presents a cell-based all-digital Tunable DQS Timing Circuit for adaptive DQS timing adjustment in 3D-DRAM interfaces. The proposed architecture consists of a four-phase Delay-Locked Loop (DLL), and Candidate DQS Selectors to generate 16 candidate DQS signals around the ideal quarter-cycle timing position. The proposed DLL performs delay locking and tracking to maintain stable timing characteristics under process and operating-condition variations. Implemented in a 40-nm CMOS process, the proposed design provides a phase-shift range from 88.99 ps to 480.80 ps with an average step size of 26.29 ps when the clock rate is 1.066 GHz. Simulation results further demonstrate that, under a TSV extra-delay condition of 250 ps where the conventional fixed-DQS-timing scheme could have failed, our design can still maintain reliable operation by selecting a proper candidate DQS signal, and thereby enhancing timing robustness for 3D-DRAM ICs.