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Warpage Simulation Development for PCB Packaging in AI Drives under Reliability Conditions
會議論文集

Warpage Simulation Development for PCB Packaging in AI Drives under Reliability Conditions

S.Z. Desai, Y.-Y. Liou, M.-C. Wu, C.-C. Tsai, C.-Y. Ma, X.-H. Chen, C.-C. Tsai, W.-C. Wu 和 C.-C. Lee
2026 International Conference on Electronics Packaging and Hybrid Bonding Symposium, ICEP-HBS 2026, 頁碼.166-167
2026

摘要

Finite Element Analysis PCB packaging Reflow reliability Warpage simulation Chip scale packages Flip chip devices Packaging Reliability analysis Soldered joints Soldering Surface mount technology Condition Finite element analyse Flip chip assemblies Manufacturing process PCB packaging Reflow reliability Simulation development Surface-mount technologies Warpage simulation Warpages Mechanical stability
Warpage can be further amplified during subsequent manufacturing processes, such as surface mount technology and flip-chip assembly, due to repeated thermal cycling and process-induced temperature histories. This deformation may result in defects including empty or weak solder joints, which directly degrade assembly yield and long-term reliability. Therefore, effective control and evaluation of substrate warpage are essential to ensure mechanical stability and manufacturing robustness. This study emphasizes the importance of warpage management in advanced semiconductor packaging and highlights its impact on product performance and reliability. © 2026 Japan Institute of Electronics Packaging.

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https://www.scopus.com/inward/record.uri?eid=2-s2.0-105043767333&doi=10.23919%2fICEP-HBS69241.2026.11550577&partnerID=40&md5=c43dd25feede9bf1d91d4663f4273cec檢視

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