Abstract
This thesis is divided into four parts to demonstrate 3D IC applicable nonvolatile memories with nanostructures. In the first part, we improves the performance and reliability of a trigate polycrystalline silicon (poly-Si) nanowires twin-TFT nonvolatile memory (NVM) by NH3 plasma passivation and O/N structure. Trigate structure significantly enhances the programming and erasing speed, but a FG NVM device can not endure cycling stress. NH3 plasma contains H and N radicals. H radicals can passivate the grain boundaries in poly-Si channel and the interface trap at Si/SiO2 interface; N radicals can be combined with Si dangling bonds at the interface to form the Si-N bands, which are stronger than Si-H bonds. After NH3 plasma passivation, the TFT performs high Ion/Ioff and steep SS; passivated twin-TFT NVM shows larger memory window and improved endurance and retention. Secondly, we use O/N structure is to replace a single SiO2 layer. Nitride film has discrete charge trapping property; only a portion of the stored charge leaks out as a stress-induced leakage path (SILP) is formed. O/N structure enhances the electric field in tunneling dielectric, so an O/N structure twin-TFT NVM shows faster programming and erasing speed than an O/structure twin-TFT NVM. Thanks to the discrete charge trapping property, an O/N structure twin-TFT NVM shows good reliability. At last, a twin-TFT NVM with InGaZnOx (IGZO) FG is demonstrated. This NVM device with a low fabrication temperature is feasible for display application. An IGZO FG NVM exhibits large memory window and good retention. In the second part, we study a pi-gate poly-Si NWs TANOS NVM. Pi-gate enhances the programming and erasing speed because corners induce higher electric field. Al2O3 has higher dielectric constant than SiO2, so TANOS can have higher αG than that of a SONOS NVM with the same blocking oxide thickness. Because TANOS NVM uses nitride CTL, it can be performed as 2 bits per cell. A kind of 2-bit operation based on F-N tunneling is demonstrated for a long channel TANOS NVM. In order to obtain high-k Al2O3, high temperature annealing is necessary. However, high temperature causes Al2O3 to be crystallized. The grain boundaries of the Al2O3 behave as leakage paths that the stored charge in nitride can leak to gate through those grain boundaries. Introducing nanocrystals (NCs) in NVM devices was reported to improve retention. We introduce Si-NCs in TANOS NVM for improving the retention. In the third part, we demonstrate a gate-all-around (GAA) structure SONOS NVM with Si-NCs charge trapping layer. GAA structure has the best gate control in multi-gate structure. GAA structure concentrates the electric field in tunneling oxide, and lessens that in blocking oxide. NCs reduce the charge loss and possess discrete charge trapping property. GAA NCs NVM shows fast programming and erasing speed, good reliability and can perform 2-bit operation. Finally, a trigate NWs TFET SONOS (T-SONOS) NVM is demonstrated. First, we introduce the trigate structure to improve the performance of a TFET. The Ion, Ion/Ioff and SS can be significantly improved by trigate. Furthermore, corners of trigate enhance the electric field for F-N tunneling. This proposed T-SONOS performs large memory window and good reliability.