Abstract
As global competition continues to strengthen in semiconductor industry, semiconductor companies strive to maintain competitive advantages through yield enhancement, productivity improvement, and cost reduction. As the shrinking feature size and the advanced technology of integrated circuit (IC), the impact of unpredictable variations of manufacturing process are increasing and leading to low yield. The low yield problem can hardly be solved by manufacturing process improvement alone, while it can be improved by design of chip modification. In particular, cause-and-effect relationship between IC designable variables and manufacturing response variables should be identified in advance. However, some of them cannot be formulated directly by physical or mathematical formula. In particular, amounts of data have been recorded during design and manufacturing process, yet meaningful information is latent behind the huge data. This study aims to develop a data mining framework of design for manufacturability (DFM), in which data mining methodology is applied to construct the casual relation as the basis of design guidelines to improve chip layout with better manufacturability. The extracted patterns or derived rules can not only help designer to validate the assumption of design variable but also be a basis of further improvement direction. Finally, two empirical studies for enhancing wafer productivity and yield were conducted to evaluate the validity of proposed framework and practical viability. The proposed framework can assist IC designer in effectively deriving chip layout design for wafer productivity enhancement. In addition, it also can provide a guideline of overlay registration layout for exposure yield enhancement with metrology cost and compensation performance taken into account.