Abstract
There is growing need for memory repair due to the introduction of more and more system-on-chip (SOC) and other highly integrated products (e.g., 3D-IC), for which the chip yield is being dominated by the yield of on-chip memories or known good dies (KGD) of commodity memories. The memory redundancy-repair schemes are quite different between commodity and embedded memories. Embedded memories are normally repaired by built-in self-repair (MBISR) schemes with only limited on-chip resource, be-cause repairing embedded memories by conventional off-chip schemes is too expensive. On the other hand, commodity memories are much larger and more complicated than embedded memories, and have much more test re-quirements to meet various applications and systems. Therefore, they are normally tested and repaired by an Automatic Test Equipment (ATE). The memory is designed with more complicated built-in redundancies, and may require more complex redundancy analysis (RA) algorithms as compared with MBISR. However, ATE is expensive. To reduce test and repair time, commercial ATEs cannot afford complex RA algorithms that consider the complete redundancy constraints. That results in certain degree of loss in repair rate, and thus yield. In this thesis, we first propose a Memory Spare-Allocation tool called MESA, based on a Constrained-Orthogonal algorithm. It provides high programmability for various memories tested by ATEs. The tool obtains fault information from the ATE output, and then generates repair solutions for the memories to be repaired by the laser repair equipment. Although the pro-posed linear-time heuristic spare-allocation algorithm is not optimal, as the problem is NP-complete, it is quite efficient and achieves a higher repair rate than the original RA algorithms on the ATE. In one of our experiments, e.g., the proposed algorithm can rescue about 22% of the dies that did not pass the original ATE repair process, effectively improving the yield. To explore various redundancy architectures and further enhance the yield, we also analyze, develop and evaluate repair schemes with silicon failure bitmaps from our industry partners. We have developed advanced redundancy analysis methods, including bitmap visualization, mathematical estimation, redundancy-oriented coverage statistics and analysis, critical and must-repair analysis, and combined index of repair rate and overhead. In the second part of the thesis, we propose an MBISR generator called BRAINS+, which automatically generates RTL-level MBISR circuits for SOC designers. The MBISR circuit is based on an RA algorithm that enhanc-es the Essential Spare Pivoting (ESP) algorithm, with a more flexible spare architecture, which can configure the same spare to a row, a column, or a rectangle to fit failure patterns more efficiently. The proposed MBISR circuit is small, and it supports at-speed test without timing-penalty during normal op-eration, e.g., with a typical 0.13 μm CMOS technology, it can run at 333 MHz for a 512 Kb memory with 4 spare elements (rows and/or columns), and the MBISR area overhead is only 0.36%. With its low area overhead and zero test-time penalty, the MBISR can easily be applied to multiple memories with a distributed RA scheme. Compared with recent studies, the proposed scheme is better in not only test-time but also area overhead.