Abstract
Increasing demand for better cell performance and reliability in VLSI memories is currently a great challenge beyond the 65 nm technology node. Emerging memories such as MRAM (Magnetoresistive Random Access Memory), PCM (Phase Change Memory), and RRAM (Resistive Random Access Memory) are promising candidates to meet these requirements, and are even targeted at stand-alone and embedded memory applications. This dissertation presents a novel contact RRAM (CR-RAM) realized by stacking TiN/TiON/SiO2 between W contact and N+ silicon, which is fully compatible with 90 nm CMOS logic technology. The proposed RRAM exhibits excellent performance in terms of a fast program speed, easy fabrication, and immunity to overwrite and non-volatility. Data retention is significantly over 1 000 hours under 150 °C baking conditions. An investigation of the self-compliance of the One Transistor 1T+1R CR-RAM (One Resistor Contact Resistive Random Access Memory) using the current bias method confirms that the reset current can be reduced by the word-line (WL) controlled set current. The random telegraph noise (RTN) generated by electron trapping/de-trapping on the stacking layers was also investigated to determine the CR-RAM switching mechanism. The RTN model makes it possible for parameter extraction from the measured data. Analyzing the extracted parameters and the measured results lead to a proposed trap-induced resistive switching model.