Abstract
Abstract High-k dielectric constant (high-k) material has been proposed to replace the conventional silicon dioxide as gate dielectrics of metal-oxide-semiconductor (MOS) devices in the near future. However, the characteristic and extent of charge trapping in the interfacial layer between high-k dielectric and silicon have been reported to affect strongly the electrical characteristics of high-k gated MOS devices. Hence, providing an accurate and quick measurement for density and distribution of interface and bulk traps is believed to be a valuable research topic. This work proposes several measurement techniques based on the principle of charge pumping (CP) and provides some discussion in depth for measurement results. A CP technique with varying fall and rise times has been successfully applied to determine the mean capture cross-section and the energy distribution of the interface-trap density Dit(E) in high-k gated MOS devices. Also, in order to further study the border traps near the high-k/Si interface, a calculation model based on the variation of the charge pumped per cycle (Qcp) with frequency has been proposed to estimate the depth profile of border trap in the high-k dielectric. Besides, the influence of border traps on CP measurement and its unique behavior are also investigated. It is found that there is a non-uniform distribution of bulk trap density existing in high-k gate stack dielectric. Moreover, the effects of amplitude of gate pulse and electrical stress-induced traps by a CP measurement are studied. Measurement results indicate that the weak bonds in high-k gate dielectric are easily trapped by charges after stressing; thus, stress results in a large threshold voltage (Vth) shift. It is also observed that the stress-induced border trap is probably not a fixed trapping center but a mobile defect like hole. By taking into account on the effect of carrier tunneling in slow oxide traps, a promising CP technique has been proposed to obtain a clear observation on the spatial and energy distribution of the near-interface traps in the gate dielectric of high-k gated MOSFETs. The CP method with varying-frequency has been shown to be more effective for probing border traps than that with varying-amplitude. Border-trap density is relatively lower in the HfSiON layer due to its better bonding.