Abstract
Error control codes or error correction codes (ECC) have been widely used to maintain the reliability of memories, but ordinary ECC codes are not suitable for memories with long codewords. For portable products, power reduction in memories with DRAM-like cells can be done by reducing the refresh frequency, but the loss of data integrity should be taken care of seriously. To solve these issues, in this thesis, we present a parallel encoding and decoding ECC scheme to reduce refresh power for an industrial pseudo SRAM (PSRAM) with long codewords. We also propose a systematic way to generate the parity check matrix and the parity correction mechanism to reduce the operating power for the proposed scheme. As for the 70ns access time of the 256MB PSRAM with the (72,64) code and 16-bit I/O, experimental results show that the new ECC scheme can be integrated with the READ/WRITE operations with about 0.2% circuit area overhead and less than 3.5ns encoding/decoding time. The parity overhead of the new ECC scheme is 12.5% instead of 37.5% as in the conventional scheme with the (22, 16) code The proposed architecture provides a flexible solution for memories with different widths of ECC codewords and I/O ports, without the error masking effect or reduction in reliability. To provide a small form factor, reduce power consumption, increase performance and memory density, three dimensional integration circuits (3D IC) seem an inevitable solution for these requirements. For the challenges of 3D IC, yield improvement is the most critical and emergency issue. Most works in 3D IC testing focus on the post-bond interconnection test. However, pre-bond test is preferred for the 3D IC, since it reduces stacking yield loss and thus saves the following cost. In this thesis, we introduce three pre-bond TSV low-frequency test schemes for blind-hole TSVs and open-sleeve TSVs by performing on-chip screening before wafer thinning and bonding. The first two schemes are for blind-hole TSVs, which have one end floating, using the charge-discharge and charge-sharing techniques, respectively, while the later is commonly seen in DRAM. The third scheme is for open-sleeve TSVs, which have one end shorted to the substrate, using a voltage-dividing technique commonly seen in ROM. By virtue of the inherent capacitive and resistive characteristics, we detect the TSVs out of a specified range as anomalies, taking into account the effects of process variations in the detection circuitry. The statistical design by Monte Carlo simulation using TSMC 65nm low-power process shows that for blind-hole TSVs, the best overkill ratio can be below 6%, but for open-sleeve TSVs, the inherent limitations restrict the applicability and the results vary. Our implementation enjoys little area overhead, requiring only a simple sense amplifier and a write buffer that are shared among a number of TSVs. Reducing the number of TSVs that share a test module will reduce the test time, but increase the area overhead. For blind-hole TSVs, the parallelism also affects the overkill and escape rates.