Abstract
In view of the challenges encountered by CMOS scaling, it seems inevitable that a highly integrated system on chip (SOC) must start from low production yield, and then it takes tremendous time and effort to improve the yield to a reasonably high level. Three-dimensional (3-D) integration can provide a means to overcome the difficulties in the design and manufacturing of these SOC products. 3-D integration has been touted as an approach to reducing the lengths of critical paths in field programmable gate arrays (FPGAs). A 3-D chip stacks a number of 2-D FPGA bare dies, interconnected by through-silicon vias (TSVs) and micro-bumps, to attain a high packing density. However, the technology also introduces new types of defects, such as TSV void and micro-bump misalignment. Testing the interconnection faults becomes inevitable. In this thesis, we establish the fault models to model these defects. Based on these fault models, we develop a fault simulator to speed up the calculation of fault coverage. We present an automatic test pattern generator for open, short, and delay faults on 3-D FPGA interconnects by exploiting the regularity of switch matrix topology and forming repetitive paths with finite steps and with loop-back. Combining the proposed build-in self-test (BIST) circuit and the test vectors, we can detect the target open, short, and delay fault on interconnects. The experimental results show that 12 test patterns suffice to achieve 100% open fault coverage for different size of the 3-D FPGAs. To detect all possible neighboring short faults needs more than 40 test patterns, whose number increases only slightly with height of the 3-D FPGA. The test patterns have high delay fault coverage (96%) for 3-D FPGAs with the number of configurable logic blocks ranging from 50×50×2 to 50×50×6, demonstrating the scalability of our method. In support of both 2-D and 3-D FPGA systems, a new BIST-based diagnosis scheme for 2-D FPGA interconnect delay faults is proposed. The faulty paths can be located after configuring the output response analyzer of the BIST circuit as a scan chain. By analyzing the faulty paths, constructing the fault map, and applying the proposed faulty segment identification algorithm, the segment fault candidates can be obtained. The proposed diagnosis scheme can find the effective test paths to locate faulty segment candidates. We also proposed a defect identification algorithm to find the test paths to identify the single and double defects. Experimental results for island-style FPGA show high diagnosis resolution in locating the faulty paths, under the single- and double- fault models caused by single and double defects, respectively.