Abstract
From the viewpoint of interfacial strength simulation, an overall reliability analysis of three-dimensional (3D) chip stacking package and the modification of the four-point bending (4PB) delamination test were investigated in this research. In the reliability analysis, aside from typical solder joint life prediction and die-crack analysis, fracture mechanics was introduced for crack examination between copper bumps, as well as copper through silicon via (TSV) and bump life prediction. Moreover, fracture analyses based on modified virtual crack closure technique (MVCCT) and finite element method (FEM) were carried out to evaluate the delamination behavior in the 4PB delamination test, and the modification for specimen size and partially-adhesive effects were proposed. For the 4PB delamination test analysis, the controlled-force loading condition for FEM models was proposed and validated. Besides, the modification for the size effect was derived through simulation predictions and experimental validation. Moreover, to broaden the critical energy release rate (Gc) measuring range when using the same substrate, the concept of partially-adhesive sandwich specimen was developed and validated. The modified equations based on the analytical solution for 4PB delamination tests were derived as well. Based on the application and validation of MVCCT in the 4PB test analysis, the former was further utilized in the fracture analysis of the 3D package. The test vehicle was mainly composed of copper TSV and bumps, and the ABF (Ajinomoto Built-up Film) lamination structure was designated. According to the vacancy observed in an actual package structure, the embedded delamination between two connecting copper bumps was evaluated to investigate the possibility of delamination expansion for the 3D package at the package level. By validating the simulation G value with the Gc value reported in literature, the delamination expansion should not happen. Moreover, the simulation procedure was performed to predict fracture behavior for the 3D package at the board level, and the results show the same conclusion as that for the package level case. In addition, three kinds of 3D package designs based on the test vehicle were developed to investigate the feasibility of mass production. In this research, several reliability issues including solder joint life, copper TSV and bump life, and die-crack were evaluated through FEM analysis for comparison between each case. The results reveal that the proposed 3D chip stacking package combined with well-developed wire-bonding and plastic ball grid array (PBGA) packaging technology yielded a relatively better performance reliability.