Abstract
As the demands for personal cameras, laptops, and smart-phones increase, development of nonvolatile memory (NVM) is rapidly expanding. NVM devices with faster programming/erasing (P/E), excellent retention and endurance characteristics are required. To achieve this goal, many methods have been applied to Charge-trapping (CT) flash memory devices. This dissertation firstly reviews the literature on CT-flash memory. According to the literature, P/E speeds can be improved by applying high-k materials to the charge-trapping layer of CT-flash memory devices. However, its poor retention that arises from the low crystalline temperature of high-k materials is an issue. To overcome this issue, a stacked structure of Si3N4 and high-k materials is proposed herein. Experimental results indicate that a stacked Si3N4/HfO2 charge-trapping layer can improve the erasing and retention operations of CT-flash devices. These improvements are attributed to the smaller valence band offset of Si3N4 to Si and the higher barrier for electron detrapping from HfO2 to Si3N4. The programming and retention characteristics of CT-flash memory devices can be further enhanced by a Si3N4/Al2O3/HfO2 as the CT layer to increase the number of injected charges that are trapped at the Si3N4/Al2O3 interface, and to provide a high barrier to electron detrapping from HfO2. Band engineering must be performed on the blocking layer to improve the performance of CT-flash memory. In this dissertation, various stacked blocking layers with various band structures are studied. The results indicate excellent data retention of devices with a sealing layer (SL) / Al2O3 blocking layer without loss of P/E speeds. The programming, erasing, and retention characteristics of CT-flash devices can be further enhanced by using the high/low/high (HLH) triple barrier structure with Al2O3/HfAlO/Al2O3 blocking layers. The effects of thickness of the blocking oxides in a multilayer barrier structure are studied by simulating the gate current density in a metal/insulator/metal (MIM) device. All MIM structures with triple insulator have the same electrical oxide thickness (EOT) and different thicknesses for each layer. Simulation results show a thin second layer for triple blocking layer with an HLH barrier structure is preferred because its gate current density is smaller. Finally, the operating characteristics of CT-flash devices with different nitrogen profiles in gate stack are studied. Two peaks in the nitrogen depth profile are formed by plasma immersion ion implantation (PIII) nitridation treatment. A shallow peak is obtained in the blocking layer and a deep peak is obtained in the CT layer. Nitrogen can passivate defects in the interface and increase the number of deep trapping sites in the bulk. Therefore, the properties of nitrogen are determined by their locations in the gate stack. The results indicate that the nitrogen profile in the gate stack is more important than the nitrogen concentration therein. A nitrogen profile that has a deep peak with a high concentration and shallow one with a suitable concentration (< 18 %) is optimal for PIII nitridation treatment.