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Characterizations of n‐channel MOSFETs with Tailored Source/Drain Extension for Mask ROM and EEPROM Applications
Dissertation

Characterizations of n‐channel MOSFETs with Tailored Source/Drain Extension for Mask ROM and EEPROM Applications

陳原逢
Doctor of Philosophy (PHD), 國立清華大學, 電子工程研究所
2011

Abstract

非揮發性記憶體 罩幕式唯讀記憶體 可電氣抹除可程式編碼唯讀記憶體 非重疊植入 淺淡摻雜 NVM Mask ROM EEPROM NOI LDD
Non-volatile Memory (NVM) has been developed and improved in past years, and recently it has been received much attention in mobile or portable applications, such as mobile phones, smart cards and digital camera. First, the history of the Non-volatile Memory (NVM) and the concept of the NVM are introduced. And the typical NVMs, such as EPROM, EEPROM, flash memory are also introduced. However, among various Non-volatile memory types, Mask programmable read-only-memories (Mask ROMs) are one of the cheapest memories. Mask ROMs are widely used memory devices capable of storing permanently information. This thesis presents a novel n-channel MOSFETs with two-bits-per-transistor and gate-to-drain non-overlap implantation (NOI) schemes for Mask ROM and EEPROM applications. The NOI mask ROM can be coded by using the lightly doped drain (LDD) implantation mask and the related processes. This simple coding scheme is fully compatible with industrial CMOS processing. The characteristics of this NOI mask ROM, including two-bit-per-transistor operation, body effect, hot carrier impact and array layouts are investigated. By sharing the same array layout and readout circuit, the potential of NOI devices’ seamless migration between the mask ROM and EEPROM functions are also demonstrated.

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