Abstract
Clock signal is the common timing reference for all synchronous sequential components in integrated circuits. The design of clock distribution network can affect a chip’s performance directly such as clock skew and power consumption. In the beginning of this dissertation, we build a fast power /ground noise simulation environment. After that, we aim to the clock design issues of two different low power techniques, and propose two architectures to resolve the problem respectively. First, we propose an IR drop simulation algorithm in this dissertation based on Preconditioned Conjugate Gradient (PCG) method. PCG has been demonstrated to be effective in solving large-scale linear systems for sparse and symmetric positive definite matrices. One critical problem in PCG is to design a good preconditioner, which can significantly reduce the runtime while keeping memory usage efficient. Universal preconditioners are simple and easy to construct, but their effectiveness is highly problem-dependent. On the other hand, domain-specific preconditioners that explore the underlying physical meaning of the matrices usually work better, but are difficult to design. In this part, we study the problem in the context of power grid simulation, and develop a novel preconditioner based on the power grid structure through simple circuit simulations. Experimental results show 43% reduction in the number of iterations and 23% speedup over existing universal preconditioners. After that, we focus on the low-power issues. Resonant clock has proposed for energy recycling in high-performance design. However, the resonant clock often suffer from area overhead because of the need to insert large decoupling capacitors. To overcome the area overhead for resonant clock, we propose a novel resonant clock mesh structure, called Ping-Pong mesh. Ping-Pong mesh contains two sub-meshes, each of which plays the role of the decoupling capacitor of the other, and the clocks in two sub-meshes operate in completely opposite phases. As the result, a Ping-Pong mesh does not need additional decoupling capacitors as in previous works. Also, Ping-Pong mesh can reduce the power-ground surge current about half of previous works. Finally, multi-power-mode design is another useful technique for lowing the chip power without sacrificing circuit speed. However, as the supply voltage is down to the ultra-low voltage level, a huge clock skew may occur among different power modes. If conventional power-mode-aware buffers (PMABs) are used to eliminate the clock skew, a large overhead on power consumption will be introduced. In this section, we propose a new PMAB architecture to save the power consumption for clock skew minimization. The proposed PMAB architecture is composed of two serially-connected sub-PMABs at two different voltage levels, respectively: in the front sub-PMAB, the low voltage level is used for coarse-grained clock skew minimization; then, in the back sub-PMAB, the high voltage level is used for fine-grained clock skew minimization.