Abstract
The popularity of power-constrained mobile and embedded computing applications is increasing rapidly. For such systems, power consumption is a key consideration to design goals because of the limited battery lifetime, and reducing power consumption represents a crucial challenge for today's software and hardware developers. In CMOS circuits, power is mainly dissipated in a gate during transitional activities --- when the gate output transits from 0 to 1 or from 1 to 0, but leakage power is representing a greater proportion of total power dissipation as the feature size of semiconductor technology continues to reduce. The problem of reducing processor power/energy consumption has been studied at physical-, logic-, and circuit-level extensively before, and now it is actively studied by architects and system software designers. In this thesis we will present investigations on how system software techniques can be used to minimize energy consumption. This includes two approaches: one emphasizes compilation techniques to insert instructions into programs to shut down and wake up function units as appropriate (i.e., not only to generate power-control instructions whenever a function unit goes `idle', but to produce a proper placement for power-control instructions so as to reduce the amount of such instructions) in order to reduce leakage energy consumption, and the other focuses on real-time scheduling problems in operating systems on a single processor (or multiple processors) with the ability to scale their operating supply voltages or even on processors with multiple voltage domains. Simulations demonstrate the effectiveness of these two methodologies. Specifically, the approach using compilers to generate power-gating controls reduces the overall energy consumption, including both dynamic and leakage energy consumption, of a processor by average of 11.9% compared with the one without power-gating mechanism, while the code size growth in terms of the amount of total instructions and the performance degradation are 25% and less than 1% on average, respectively. In the other approach that involves a real-time scheduling with variable supply voltages, the average normalized energy consumption of three real-world applications (CNC, GAP, and videophone) under an eight-voltage-level system is 53.74%, 37.81%, and 13.10%, respectively. Moreover, it has averages of 45% and 20% reduction of AES and RSA modules compared with an ordinary scheduler without energy consideration, respectively, when applying the approach on a specific security processor. We also address the potential issues when combining both compiler and operating system techniques for power management.