Abstract
It is a common understanding that there is a performance gap between the processor and the DRAM in a computer system, which is called the memory wall. The memory wall can become more and more serious if not properly addressed by researchers and practitioners. Therefore, in addition to the improvement of the processor-DRAM interface, there is also drastic need in performance enhancement of the DRAM itself, from device, circuit, to architecture. New DRAM designs need to be developed, and the DRAM modeling tools are crucial to design exploration and evaluation. The existing modeling tools used in design exploration are not efficient enough so far as closing the gap is concerned. Also, there is a lack of flexibility for such tools to explore different architectures. In this thesis, we introduce the notion of component and propose a component-based DRAM modeling method. In this method, we abstracted a DRAM design with a framework, containing the DRAM architecture at the component level, the arrays, the floorplan, the whole chip, and the interface. Based on the abstraction, a modeling tool has been developed to accurately predict the silicon area, delay, and power of the DRAM with high architecture flexibility and short computation time. Our tool has been used for modeling state-of-the-art DRAM designs not supported by the prior works. We also have improved the traditional RC-delay model and CV-charge model to achieve higher accuracy. The modeling accuracy is verified by a commodity DDR2 DRAM in our experiment. With the component-based approach, we also propose a generalized- architecture exploration algorithm, in which we introduce the concept of variable links, representing the relation between the variables. By dealing with the variables and their links, our method can expand the exploration space with the proposed algorithm to reduce the complexity. In our collaboration with ITRI, this method has successfully identified the full array architecture candidates for a DRAM test chip, which is a TSV-based 3D DRAM die (to be used for DRAM die stacking) with a low latency of 10ns and high bandwidth of 100GB/s. We also have used this method to find the array style that has higher potential for the Wide-IO interface than the traditional one. The modeling and exploration approach proposed in this thesis provides system designers with a way to efficiently identify a better DRAM memory system to minimize the memory wall.