Abstract
With increasing demands for higher data rate and better services, more efficient and advanced modem techniques are being adopted by many wireless standards. However, to achieve this goal, the design of RF transceiver towards more and more critical. Instead of doing the RF transceiver design in pure analog way, we propose several digital calibration techniques to cooperate with the analog RF transceiver and these digital compensation techniques help to correct for the analog imperfections which in turn improve the overall RF transceiver performance. Several digital signal processing-assisted (DSP-assisted) error compensation techniques are reported in recent years to solve the in-phase/quadrature (I/Q) imbalance problem in a quadrature transceiver and achieve outstanding performance because of their high precision in system control and their excellent °exibility in circuit adaptation. However, some common drawbacks exist in these DSP-assisted techniques: 1) extra hardware cost is required on collecting feedback information for DSP, 2) the I/Q imbalance of the remote transmitter is impractically assumed to be perfectly tuned, 3) signal distortion introduced in the feedback link for DSP is irreversible, and 4) additional on-line DSP training is required. In chapter 2 of this dissertation, we propose a novel DSP-assisted scheme to compensate the I/Q imbalance jointly for the transmitter and the receiver, and at the same time to eliminate the drawbacks mentioned above. The advantages of the proposed scheme, in terms of its high accuracy, low complexity, and suitable for practical applications, will be demonstrated through analyses and extensive computer simulations. Digital predistortion at baseband is an effcient and low-cost method for the linearization of a power amplifier (PA) in a wireless system employing a non-constant- envelop modulation scheme, so as to reduce the adjacent channel interference. The polynomial and the look-up table (LUT) predistortion schemes are two commonly-used approaches. However, in each of both approaches, to reach an satisfactory adjacent channel power ratio (ACPR) in the PA output signal, people usually ends up with a complex system having the involved algorithms converge rather slowly. In the chapter 3 of this dissertation, we propose a low-complexity joint-polynomial-and-LUT predistortion PA linearizer, where the two mutually-dependent predistortion schemes can skillfully help each other. Simulation results show that the proposed joint linearizer can reduce the algorithm convergence time while achieving an excellent ACPR. Digital-to-analog converters (DACs) are essential components in communication system and are inherent nonlinear when high resolution DAC is designed. Chapter 4 of this dissertation presents a digital background self calibration technique for high- resolution current-steering CMOS DACs. The DAC core uses a true background self- calibration technique to obtain 14-b accuracy while simple analog current cell design is retained. The proposed digital background calibration technique can resolve the inherent drawbacks in the popular calibration schemes and make the calibration scheme more applicable to practical implementation. The DAC with background calibration loop trims the static performance to less than 0.55 LSB. The DAC achieves maximum spurious free dynamic range (SFDR) of 81 dB for an input frequency of 1.6 MHz and 67 dB for an input frequency of 48.75 MHz at a sampling rate of 150 MS/s. The DAC is implemented in a 0.35 ¹m CMOS process and occupies active area of 2.4 x 1.1 mm2. At 150 MS/s power consumption is 165 mW from a 3.3-V power supply.