Abstract
Facing a multitude of design constraints: higher design complexity, immature new process technology, shrinking time-to-yield, etc., designers have to take debug and diagnosis as an integral part of the design process. Yet, imposed by the huge design size, efforts of diagnosis increase rapidly. Diagnosis tools are used to quickly shrink the number of defective candidates that helps to speed up the process without resorting to physical inspection tool for every possible suspect of faulty location. In advanced process, timing defects comes from several aspects such as dustinduced short, open defects induced by in inappropriate Design For Manufacturability (DFM) rules, lens aberration from lithography system, variation on dopant concentration or critical dimension from Chemical-Mechanical Polishing (CMP) process, etc. Therefore, it is getting more and more difficult to identify the main causes of timing failures from such a wide range of suspects. In this thesis, we propose a series of diagnosis methods targeting on not only spot delay defects but small delay variation induced by process variation. The proposed method is capable of estimating delays of segments in tested paths instead of just reporting the ranks of segments as the traditional diagnosis methods. With the capability, a timing profile for the process and the die under manufacturing can be extracted based on the estimated segment delays. Moreover, the causes of process variation can be concluded by applying machine learning techniques on diagnosis data. With the proposed feature encoding and ranking method, the main features of abnormal devices for a failing chip instance can be extracted. In the experiments, 1.96 of first-hit-rate (ranking of the injected defects) for single spot defects and 1.43 of first-hit-rate for 10 spot defects simultaneously injected can be achieved For process variation induced small delay variations, the proposed method can provide an accurate estimation of segment delays. On average, 0.916 of correlation between estimated and sampled segment delays for a dozen of benchmarks.