Abstract
As leakage power has become a major contributor to the total power consumption, power gating has been a very effective method among leakage reduction techniques. In this dissertation, we propose three important design issues for optimization of power gating design. One important design issue for a power gating design is to limit the surge current during the wakeup process. Normally, a wakeup scheduling which is required to control turn-on times of sleep transistors should be well-designed. We propose a new wakeup scheduling formulation which considers the trade-off between wakeup times and hardware resources. Second, for a modern power gating design, the number of modules that need to be turned on and their locations may vary depending on the task to be performed at runtime. Accordingly, the important issue is the wakeup scheduling for the module-level power gating design. To the best of our knowledge, this is the first in-depth study on on-line module-level wakeup scheduling for high-performance architectures. Last, since PMOS sleep transistors in the functional mode are turned-on continuously, Negative Bias Temperature Instability (NBTI) influences the lifetime reliability of PMOS sleep transistors seriously which leads to the performance degradation of the power gating design. We present a novel NBTI-aware power gating architecture to extend the lifetime of PMOS sleep transistors.