Abstract
As MOSFETs scale into nanoscale regime, extensively minimizing source/drain depth limits the improvement of driving drain current due to the increased series resistance. By eliminating implanted ultra-shallow junctions, the metallic Schottky Barrier MOSFET (SBMOS) becomes a most attracting candidate in deep sub-50 nm regime. The objective of this dissertation is to explore in depth the design and application of SBMOS devices using two-dimensional numerical simulations for the use of SBMOS in future CMOS technologies. The current-voltage characteristics of SBMOS are highly dependent on Schottky barrier height, source/drain to gate misalignment, and gate-oxide thickness. Ambipolar conduction of SBMOS can be optimized by an appropriate choice of these primary parameters. A dopant segregated layer can efficiently modify the Schottky barriers to suppress the off-state ambipolar conduction and simultaneously to enhance the on-state driving current. However, apparent degradations of ambipolar conduction in SBMOS are observed when a thin gate-insulator or a heavy halo profile is used for scaled short-channel devices. A novel Dual Workfunction Gate architecture is innovated to optimize SBMOS by tailoring Schottky barrier distributions through vertical gate engineering. An optimal SBMOS can be achieved with enhanced driving current, minimized ambipolar conduction and suitable short-channel effect. This study also elucidates the latent noise mechanisms in SBMOS devices. The complex noise problems in SBMOS arise from the particular ambipolar conduction and the additional interface states at metallic source/drain junctions. In addition to the excess noise of conventional MOSFETs, the interface traps at the metallic source/drain are keys to the overall noise characteristics of SBMOS. Most possible noise sources under various operating conditions are summarized herein to provide a comprehensive understanding of how noise potentially limits the practical applications of SBMOS devices.