Abstract
Multicarrier modulation (MCM) techniques have received great attention in communication systems design in recent years. One famous form of digital implementation of MCM is discrete multitone (DMT) modulation emanated from Stanford University. DMT modulation has been used or investigated for high-speed data transmission on existing twisted-pair phone lines (copper wires). For example, the DMT technique has been selected by the American National Standards Institute (ANSI) and the European Telecommunication Standards Institute (ETSI) for asymmetric digital subscriber lines (ADSL) service which can provide several megabits of data transmission per second on ordinary phone lines. Moreover, ANSI and ETSI have adopted the DMT technique for future very high-speed digital subscriber lines (VDSL) service whose data date would be as high as 52 megabits per second. One inherent problem in implementing a DMT-based ADSL or VDSL transmission system is that the modulator and demodulator involve respectively very complicated inverse discrete Fourier transform (IDFT) and discrete Fourier transform (DFT) computations, where the transform length may be 512 or 4096. Therefore, it is highly desirable to develop efficient algorithms and structures for the modulator and demodulator of ADSL/VDSL transmission systems. In this thesis, some solutions to these problems are proposed. In the first part of this dissertation, we present two new VLSI architectures for fast computation of the N-point DFT and IDFT based on a radix-2 fast algorithm, where N is a power of two. The first architecture consists of one complex multiplier, two complex adders, three special two-port RAM’s of N/2 (complex) words each, one ROM of N/2 (complex) words, and some simple logic circuits. It can compute one transform sample every log2N+1 clock cycles on an average. In the case of N=512, the throughput is up to 4M transform samples per second using 0.6 mm CMOS technology. Such a processing speed makes it rather attractive for use in ADSL systems. The second architecture is an improved version of the first design, where the complex multiplier used is 100% efficient in utilization and the throughput is doubled (one DFT sample per 0.5´log2N clock cycles) with an increase of two RAM’s of N/2 words each. Based on 0.35 mm CMOS technology, the chip is capable of operating at a 100 MHz clock rate to compute 22.2M transform samples per second in the case of N=512, which meets the speed requirement of VDSL applications. In the second part of this dissertation, we present two novel discrete Hartley transform (DHT) based VLSI architectures for quickly computing the N-point DFT and IDFT, where N is a power of two. The first architecture makes use of one real multiplier, three real adders, four special two-port RAM’s of N/2 (real) words each, one ROM of N (real) words, and some simple logic circuits to yield, on an average, a throughput of one DFT sample per log2N+2 clock cycles or one IDFT sample per log2N+1 clock cycles. Using 0.6 mm CMOS technology, the proposed design can reach a throughput of 4M DFT samples per second or 3.6M IDFT samples per second in the case of N=512. Such speed performance makes it pretty suitable for use in ADSL systems. The second architecture is an improved version of the first design that can achieve a double throughput (one DFT or IDFT sample every (log2N+1)/2 clock cycles) with an increase of one real multiplier and two N/2-word RAM’s. For the purpose of verification, a prototype chip of the improved DHT-based design is fabricated for computing the 512-point DFT/IDFT. The chip is based on a standard cell library for 0.35 mm CMOS 1P4M technology and it is capable of operating at a 100 MHz clock rate to compute 20M transform samples per second. The low-complexity and high-throughput features make this chip well suited to real-time VDSL applications. The third part of this dissertation presents a real-valued discrete MCM approach that is based on the use of the DHT and the corresponding inverse transform (IDHT) to perform the modulation and demodulation operations. Since the DHT and IDHT definitions are identical, we can use the same hardware or program to implement the modulator and demodulator of the proposed MCM method. As compared to the complex-valued DFT-based MCM method, the proposed one achieves the same transmission performance with reduced computational complexity and implementation cost. To realize the proposed real-valued MCM method, the architectures described in the second part of this dissertation can be applied directly. From both of the implementation and performance points of view, the proposed approach would be a promising alternative for designing future MCM-based communication systems.