Abstract
Recently, physical limitations restrict the development of microelectronic industry following Moore’s law. To achieve high performance, small form factor and lightweight application, the electronic packaging has developed following more than Moore’s law which is fulfilled by system-in-package (SiP) or 3D packaging approaches. This research proposes a double-chip stacking structure in an embedded fan-out wafer level packaging (WLP) with double-sided interconnections. It can resolve the problem of assembling fine-pitched chip to coarse-pitched PCB through redistribution layer (RDL). The thermal performance of the proposed packaging structure is examined and discussed by using finite element (FE) analysis. The thermal performance of the WLCSP is compared with the proposed structure. It indicates that the thermal resistance is reduced from 49 °C/W to 39 °C/W, because the proposed packaging structure has a larger size silicon carrier to improve the capability of heat dissipation. According to the thermo-mechanical behavior of the double-sided with double-chip stacking structure during thermal cycling loading, the overall reliability assessment for solder joints and RDLs through FE analysis are studied. The application of soft lamination material and the selection of carrier material whose CTE is close to that of PCB can effectively enhance the reliability of solder joints more than 1,000 cycles. Base on the proposed design guideline, the large dies and NAND stacked flash dies are successfully applied on the proposed structure, and the life time predicted in this research is accepted by most electronic packaging industries. Besides, the double-side capability is applied on the proposed structure; the first and second RDLs are established in FE model. The strain values of the first RDL are not varied along with changing of trace layout. Stiff passivation material can prevent the deformation of the first RDL caused by out-of-plane movement to diminish the equivalent plastic strain at copper via. For the second RDL, the direction of the trace/pad junction which is parallel to the major direction of the CTE mismatch is recommended. The curved portion can absorb the expansion of metal line and filler material, and the stress concentration happens at via is reduced. The design-on-simulation (DOS) methodology is necessary in developing novel packaging structure in the electronic packaging industry. The overall design, thermal analysis, and structural reliability assessment for future microelectronic packaging can be analyzed through numerical method with suitable validation. The analytic procedure can effectively reduce time-to-market and fabrication cost of new electronic devices.