Abstract
This dissertation presents two K-band transmitter front-ends and a W-band wide tuning range PLL for automotive radar applications with different standards. These circuits are all implemented in CMOS technology aiming for low cost, high integration level, and desired functionality. First, a K-band ultra-wideband (UWB) pulse-compression (PC) automotive radar transmitter in 90 nm CMOS is presented, which is composed of the fully-integrated pulse generator, mixer, driver amplifier, phase-locked loop (PLL), and timing circuitry. The PC technique with coding gain can effectively enhance the detection resolution and also improve the signal-to-noise ratio. We propose a PC transmitter allowing fast and precise code generation with small power consumption and chip area, and also offering reconfigurable capability. Compared with previously reported UWB pulse radars with relatively simple coding schemes, the proposed transmitter features a much more challenging 15-bit pseudo noise (PN) code design using high speed shift registers, which can improve signal-to-noise ratio (SNR) up to 23.5 dB. The measured results demonstrate correct output waveforms corresponding to different modulation codes with the spectrum well confined under the regulation mask. With a modulation rate over 3 Gb/s (pulse repeat frequency of 6.125 MHz), a resolution of ~ 5 cm can be achieved. Second, a K-band UWB PC automotive radar transmitter modified based on the first work is presented. This design proposes the bandwidth extension and pulse shaping techniques to further improve the performance of the transmitter. The conversion of non-return zero (NRZ) to return zero (RZ) signal format is performed in each bits of compressed pulse. The bandwidth of the output pulse can be doubled, leading to increased resolution of radar systems. Besides, a pulse shaping technique is employed based on an adjustable low-pass filter. The pulse shaping technique can reduce the peak power of side lobe of the PC pulse to satisfy the FCC mask regulation and also enhance the spectrum efficiency. The output spectrum of PC pulse will be well-confined in the FCC mask to improve the SNR of the radar system. Under the a reduced modulation rate of 1.5 Gb/s (only half rate compared with that in the first work), a same resolution of ~ 5 cm can be achieved. Also, the proposed pulse shaping can reduce the peak power of side lobe by 5 dB. Finally, a wide tuning range W-band phase-locked loop (PLL) in 90 nm CMOS is presented. A novel frequency tripling topology with a single cross-coupled pair and a dual tank is proposed for the voltage-controlled oscillator (VCO) to achieve wide tuning characteristics under low power consumption. The locking range of the PLL at the fundamental tone is 25.4–29.7 GHz, and an excellent tuning range at the third harmonic frequency up to 12.9 GHz (from 76.2 to 89.1 GHz, 15.6%) is obtained. Under a 1.2 V supply voltage (Pdiss= 62.4 mW), the measured closed-loop phase noise of the PLL is 83.5 dBc/Hz at 78.34 GHz. To the best of our knowledge, the achieved turning range is the highest currently reported for the PLLs operating in a similar frequency range in CMOS technology.