Abstract
As the semiconductor industry approaches the limits of traditional silicon complementary metal-oxide-semiconductor (CMOS) scaling, introduction of novel materials and innovative device structures has become necessary for the future of CMOS. High dielectric constant (high-k) material has been proposed to replace the conventional silicon dioxide as gate dielectrics of MOS devices. High mobility materials are also being considered to replace Si in the channel to achieve higher drive currents and switching speeds. Ge has particularly become of great interest as a channel material, owing to its high bulk hole and electron mobilities. However, the characteristic and extent of charge trapping in the interfacial layer between gate dielectric and silicon have been reported to affect strongly the electrical characteristics of high-k gated MOS devices. Hence, providing an accurate and quick measurement for density and distribution of interface and bulk traps is believed to be a valuable research topic. This work proposes several measurement techniques based on the principle of charge pumping (CP) and provides some discussion in depth for measurement results. A modified CP technique with dynamic drain bias and various gate pulse frequencies is proposed to characterize the distribution profiles of trap generation induced by channel-hot-carrier stress in MOSFETs with high-k gate stack. With dynamic drain biases, the drain depletion region during accumulation can be modulated. Hence, the trap distribution with respect to both dielectric depth and channel location can be characterized as well. The trap generation caused by channel-hot-carrier and constant voltage stresses is also compared. Results indicate that the generation of border trap induced by CVS is small and random distributed though whole channel, while that induced by CHC stress is large and localized around the gate-edge region inside the high-k dielectric. In another study, a stress-and-sense charge pumping (SSCP) technique is proposed to measure the stress induced interface trap (ΔNit) in real time evolution without stress interruption. Results show that the ΔNit measured by this SSCP technique is much higher than that measured by the conventional method. This difference is resulted from the recovery induced by stress interruption during the sensing measurements. The ΔNit measured by SSCP method after interruption is approximately equal to that by the conventional one. The stress induced threshold voltage shift (ΔVth) and ΔNit under varies stress frequencies and duty cycles are also measured. The ΔVth seems to depend on the total stress time of stress pulse only. The ΔNit measured by SSCP with different frequencies and duty cycles are similar. The ΔNit also depends on the total stress time of stress pulse, but not the off time during the non-stress half cycle. In the last study, the interface trap density, bulk trap density and stress induced trap generation of Ge-pMOSFETs with ZrO2 and HfON dielectrics are extracted and compared by CP technique with short transition time and various frequencies. Results show that ZrO2 device has higher interface trap density but lower bulk trap density than HfON device, which implies that ZrO2 device has inferior Ge/dielectric interface but high quality dielectric bulk. The improved reliability characteristics in ZrO2 device can be attributed to the low preexisting bulk trap density which greatly suppress charge trapping in the dielectric bulk.