Abstract
Recently, CMOS device cutoff frequency and maximum oscillation frequency rise to Giga hertz due to the aggressively scaling of semiconductor technologies. Therefore, the highly integrated circuits combing both analog and digital circuits become possible. With the increasing complexity in circuit functionalities, circuit reliability testing and evaluation can be no longer following the conventional method. Conventional reliability assurances through the setting a safe operation region by device lifetime projection is insufficient to meet the demand of today’s IC and nano-scale CMOS technologies. In this dissertation, device degradation mechanisms and oxide reliability are investigated extensively. The device degraded characteristics in both the dc and the small signal characteristics up to Giga hertz are observed. From analyzing the device degradation characteristics, a sub-circuit model for describing the device degradation behavior is proposed. This model predicts both the device dc and small signal behavior in a good agreement with measured data. Several circuit blocks for RF receiver, such as Low-Noise Amplifier, Mixer, Voltage-Controlled Oscillator and Power Amplifier are designed to discuss the performance shift as a result of degradation after operational stress. A 5GHz CMOS receiver is designed to investigate the effect of each building block on reliability of receiver system. Using the established sub-circuit model, a redesign of the most vulnerable circuit block in a receiver system, the LNA, is performed. In this dissertation, the reliable evaluation method provides the circuit designers an additional degree of freedom in determining its safe operation conditions and rooms for enhancing both the circuit performance and reliability robustness. The simulated results of the redesigned LNA provide direction for more reliable system design while maintaining the highest circuit performance level.