Abstract
In this thesis, three methods to enhance the ESD robustness and an ESD CDM evaluation method are proposed. For device level, an ESD self-protected strategy for high-voltage LDNMOSFET is studied. For circuit level, layout schemes for input buffer along with VFTLP testing method are investigated. For packaged IC chip level, the influence of the bonding wire and substrate capacitance on the CDM-robustness are explored. In view of conventional high-voltage (HV) LDNMOSFETs easily damaged by low level ESD stress due to non-uniform turn-on, in this work, a new enhanced displacement-current triggering by adding floating P+ diffusions at each source finger edge for the HV LDNMOSFETs is proposed. By the minor layout modification without increasing chip size, in our experiment, with a total width of 1600 m, the HBM/ MM ESD performance improvements from 1.5 kV/ 150 V to 5.5 kV/ 450 V are achieved. In this work, the influence of the body layout on the CDM failure site and the robustness of the input buffer is explored. The CDM current flows through the gate oxide via the body and the source of the transistor, since both connect to the Vss bus line. Changing the body layout of the input buffer transistor varies the failure location of gate oxide damage and improves the CDM robustness from +150 V to +500 V. In this study, we found a correlation between very fast transmission line pulse (VFTLP) data and CDM test result. A scheme for how to utilize VFTLP data to design an input buffer circuit with CDM ESD protection is reported. In this work, the fact that the dynamic-characteristic impedance of the ESD device under VFTLP testing is independent of the stress current is found. Since both VFTLP zapping and the CDM discharge are nanosecond events, the dynamic-characteristic impedance of the ESD device can be used to evaluate the CDM threshold voltage of the input buffer based on the equivalent and simplified RLC circuit. Finally, in this work, from our experimental measurements, we found that the largest capacitance for a packaged IC chip comes from the capacitor CSUB between the die-attach plate and the metal bus line. The resistance of RSUB between the back side of the chip and the Vss pad is more than 500 . The influence of CSUB is more than that of RSUB on the CDM-robustness of the packaged IC chip, because the P-substrate of a packaged IC chip can be treated as a substrate capacitor during a CDM event, not a resistor. In addition, it is also found that by adding a bonding wire between the die-attach plate and the Vss pin, a parallel inductor to the CSUB can be created. The CDM-robustness for the packaged IC chip is further improved from + 250 V to + 375 V because of this parallel LC circuit which reduces the CDM discharge current. We also got the same trend from the Hspice simulation results.