Abstract
The SoC designs can integrate digital, memory, analog, and even RF components on the same chip. This trend greatly complicates the design of automatic test eauipment (ATE), which has to test all the components of the SoC, with higher frequency, pin count, and timing accuracy as compared with previous-generation ATEs. To address the cost and performance issues faced by conventional ATE, the HOY approach has been proposed, with two main features. One is wireless test access, and the other is embedded test. However, since HOY is a new methodology that will likely change the entire infrastructure, a detailed analysis of its cost and performance figures is necessary before deployment. In this thesis, we briefly present the HOY test system, then propose a test cost model to compare the HOY approach and the conventional test method. In a 512Mb DDR2 DRAM case, the test cost of HOY method is reduced by 74% compared with the conventional test method. The second example is a network security processor. Although in this particular case the test cost of HOY method is reduced by 21% compared with the conventional test mehod, 93.12% of test cost is spend on area overhead caused by logic BIST. If we reduce the area overhead of logic BIST, it will gain more benefit by using the HOY method. The third example is the extended version of the second example. It assumes the DUT has its own logic BIST in conventional test. The test cost of HOY method is reduced by 56% compared with the conventional test method. We found that the probe card cost becomes the bottleneck of conventional test. The ratio of probe card cost increases when the test time decrease. In addition, we analyze the test cost model with respect to different manufacturing process, area overhead, die size, manufacturing volume, and test time. Results are shown for a latest HOY prototype.