Abstract
Polycrystalline channel flash memory device has been studied for the application of three-dimensional (3D) NAND integration. For better device characteristics and continuous scaling, any methods have been proposed such as α-Si crystallization, nanowire (NW) channel and bandgap-engineered (BE) dielectrics. In this dissertation, effects of BE tunneling layer composed of nitrogen-rich (N-rich) SiN/SiO2 and low temperature (LT) N-rich SiN/ SiO2 stack are investigated on bulk capacitor device first. Devices with BE tunneling layer show faster programming and erasing (P/E) speeds but a little degraded retention performance. In the next study, a BE trapping layer composed of HfO2/SiN (HN) stack is applied to polycrystalline silicon (poly-Si) devices with planar and NW channel. Compared with the SiN trapping layer device, P/E speeds are improved by HN stacked trapping layer and the improvement is more effective on NW channel device. The retention performance of devices is also improved because of the lower conduction band level of HfO2. In the third study, HN stacked trapping layer is applied on both inversion-mode (IM) and junctionless-mode (JL) poly-Si flash device. With HN stacked trapping layer, JL device performs faster programming speed and comparable erasing speed with that of IM one, which is rarely seen in reported works which apply SiN as trapping layer and present slower erasing speed of JL device. Retention and endurance performances of JL device are also better than those of IM one. Apart from the applications of BE and JL configuration on poly-Si flash device, characteristics of poly-Si device with SiGe buried channel are also studied. P/E speeds and endurance performance are improved by SiGe buried channel without degrading the retention performance. In the next study, pure polycrystalline germanium (poly-Ge) JL flash memory device is proposed for lower fabrication temperature and complexity. The JL configuration is formed by the naturally p-type doping of poly-Ge film such that no additional implantation and activation are needed. Good operation characteristics are also observed. In the final study, a stackable vertical gate structure is demonstrated for 3D memory integration. It is found that the P/E speeds and reliability performances of top and bottom devices are similar. Small program disturb and large disturb-free window are observed with the 50-nm thick SiN isolation layer. The 3D stackable structure is also compatible for the integration with BE and different polycrystalline channel.