Abstract
System-on-chip (SOC) design methodology is becoming the mainstream in the IC industry. Integrating reusable cores from multiple resources is essential in SOC design to reduce design time. To design and manufacture SOCs with reasonable cost, however, many challenges including design, test, and yield must be overcome. In particular, memory cores are most widely used cores in SOC designs. Thus memories usually represent a significant area of the chip and dominate the yield of the chip. Diagnosis technique plays a key role during the rapid development of the embedded memories, for catching the design and manufacturing failures and improving the overall yield and quality. Investigation on efficient diagnosis algorithms is very important due to the expensive and complex fault/failure analysis process and low accessibility of embedded memories. In this thesis we present efficient techniques for SOC testing, memory testing, and memory diagnosis. In the first part of this thesis, we present a hierarchical test methodology for SOC. It supports the IEEE P1500 and 1149.1 (JTAG) wrapped cores. A hierarchical test manager (HTM) is proposed to control the test process of these cores. A memory built-in self-test (BIST) interface is also presented, which connects the HTM and the memory BIST circuit. The BIST circuit can be controlled by the serial interface or the parallel test access mechanism (TAM). The proposed hierarchical test control scheme has low area and pin overhead, and high flexibility. An industrial case has been experimented using this scheme. The results show that the area overhead of the test wrappers and hierarchical test control circuitry are about 5.1% and 0.63%, respectively. In the second part of this thesis, we propose March-based RAM diagnosis algorithms which not only locate faulty cells but also identify their types. The diagnosis complexity is O(17N) and O((17 + 10B)N) for bit-oriented and word-oriented diagnosis algorithms, respectively, where Nrepresents the address number and B is the data width. Using the proposed algorithms, stuck-at faults, state coupling faults, idempotent coupling faults and inversion coupling faults can be distinguished. Furthermore, the coupled and coupling cells can be located in the memory array. Our word-oriented diagnosis algorithm can distinguish all of the inter-word and intra-word coupling faults, and locate the coupling cells of the intra-word inversion and idempotent coupling faults. With additional 2B-1 operations, the algorithm can further locate the intra-word state coupling faults. With improved diagnostic resolution and test time, the proposed algorithms facilitate the development and manufacturing of semiconductor memories. In the third part of this thesis, two efficient March-like test algorithms for Content Addressable Memories (CAMs) are proposed first. In addition to typical RAM faults, they also cover CAM specific comparison faults. The first algorithm requires 9N Read/Write operations and 2(N +W) Compare operations to cover comparison and RAM faults (but does not fully cover the intraword coupling faults), for an NxW-bit CAM. The second algorithm uses 3N log2W Write and 2Wlog2W Compare operations to cover the remaining intra-word coupling faults. Compared with the previous algorithms, the proposed algorithms have higher fault coverage and lower time complexity. Moreover, it can test the CAM even when its comparison result is observed only by the Hit output or the priority encoder output. Fault-location algorithms are also developed for locating the cells with comparison faults. Finally, a programmable BIST circuit is proposed, which can be used for different test algorithms with various fault coverage requirements. It supports production test as well as engineering/diagnostic test. Its hardware overhead is low—about 2,540 gates for an 8k64-bit CAM. In the fourth part of this thesis, we present two data compression techniques that can be used to speed up the transmission of diagnostic data from the embedded RAM BIST circuit that has diagnostic support to external tester. The proposed syndrome-accumulation approach compresses the faulty-cell address and March syndrome to about 28% of the original size on average under the March-17N diagnostic test algorithm. The key component of the compressor is a novel syndrome accumulation circuit, which can be realized by a CAM. Experimental results show that the area overhead is about 0.9% for a 1Mb SRAM with 164 faults. A tree-based compression technique for word-oriented memories is also presented. By using a simplified Huffman coding scheme and partitioning each 256-bit Hamming syndrome into fixed-size symbols, the average compression ratio is about 10, assuming 16-bit symbols. Also, the additional hardware to implement the treebased compressor is very small. The proposed compression techniques effectively reduce the memory diagnosis time as well as the tester storage requirement.