Abstract
In this thesis, we explore two essential topics required for a successful circuit timing optimization. The first topic is a fast but accurate timing analysis while the second topic is the functional flexibility so as to achieve timing optimization and functional correction of a design. First of all, the accurate timing is extremely crucial in the advanced VLSI design process for the circuit optimization. To improve the run time of a timing analysis engine, we first present a very efficient formula of timed Boolean characteristic functions for timed automatic test pattern generation and circuit delay computation. With this very efficient analysis tool, we then present a timing analysis approach for power gating designs considering the decoupling capacitance insertion and the time-varying IR drop issue. In addition, to improve the timing of a circuit, we propose to optimize the circuit by utilizing the flexibility from functional correlations. Using the flexibility of the clock gating, we propose an iterative optimization technique to minimize the overall timing for a sequential circuit. Using the flexibility of tying inputs to Vdd or Gnd, we propose an iterative method to generate feasible mapping solutions for the EC problem.