Abstract
Throughout the technology development history of NAND Flash memory, the lower chip cost achieved by higher density array is the main driving force for further evolution. For conventional planar 2D NAND, when the critical dimension (CD) is shrunk to 10nm node, it will inevitably encounter numerous challenges in terms of degraded device performance and complex process modules, such as SAQP (Self-Aligned Quadruple Patterning) scheme. In order to keep pursuing more competitive NAND Flash memory, 3D (three dimensional) NAND Flash technology has been rapidly developed in recent years. 3D NAND Flash memory can improve the device performance by designing a larger cell size. Moreover, it can also achieve lower bit-cost based on the concept of “multiple-layer stack and one critical etching”. Unlike the cell size is relentlessly shrunk in the conventional NAND technology, the 3D NAND Flash memory stacks plural memory layers with relaxed cell size and divides each device by a deep etching scheme, which makes it as a high performance and low cost chip. Via this concept, NAND technology could be effectively scaled in an economic way. Among the 3D NAND Flash architectures ever proposed, each one owns its merits and demerits. After systematic comparison, it is found that the Vertical Gate (VG) type 3D NAND architecture possesses the superiority of smaller cell size than that of Vertical Channel (VC) one. Besides, the sensing current of this architecture will not be degraded when stacking more layers vertically. Therefore, this work analyzes and optimizes the special effects encountered inherently in the VG-type 3D NAND architecture. In Chapter 2, the VG-type 3D NAND array design and structure will be introduced. Furthermore, the corresponding operations and the decoding methods are also revealed in Chapter 2. As to Chapter 3, the “split-page” architecture that previously proposed by Chen et al., will be reviewed and its array efficiency will be discussed. Then we will propose a new string decoding scheme, named stagger string select line (stagger SSL) scheme, to improve the array efficiency from 71% to 81%. The corresponding operations and electrical data of this scheme will also be studied therein. Stagger SSL scheme is a promising method for cost-effective design of VG-type 3D NAND architecture in the future. In 3D NAND process, the process capability of the critical etching module is limited by the highest aspect ratio (AR) that could be achieved by the etching tool. Thus, for a given stack height, we will obtain a higher array capacity by scaling down the thickness of each memory layer. In Chapter 4, the Z-pitch (one poly-silicon and one oxide) reduced from 60nm to 18nm were successfully demonstrated by using two-layer devices. However, the memory margin and read current are degraded accordingly when shrinking the Z-pitch. As to the mechanisms of memory margin degradation, both “Z-interference” and “Z-disturbance” are introduced to explain the Vt (threshold voltage) shift of inhibited transistor. Among them, Z-interference is the major killer of memory margin. Hence, the Z-interference is analyzed in detail in Chapter 5 by eight-layer devices. Aided by simulation verification, the experimental data are analyzed to propose a suitable Z-pitch as the baseline for fabricating VG-type 3D NAND. In addition, several approaches are discussed to suppress the Z-interference and enlarge the memory margin. Not only the Z-pitch factor but also the horizontal distances can directly affect the device performances. Among various horizontal distances, one important parameter is the distance between edge word line (WL) and ground select line (GSL) or string select line (SSL) transistors. In Chapter 6, the distance effect on VG-type 3D NAND array operations, including read current, erase speed, and programming inhibition performance are discussed. Based on experimental and simulation data, the suitable distance will be summarized as a design guideline in the end of Chapter 6. Finally, we will conclude the results from Chapters 3 to 6 to provide important guidelines on the perspectives of fabrication aspect and design aspect. Through these studies, we can well understand its merits and limitations of VG-type 3D NAND architecture.